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1 rev. 4116h?aero?06/03 features full range of matrices up to 270k available gates 0.5 m drawn cmos, 3 metal layers, sea of gates ram and dpram compilers library optimized for synthesis, floor plan and automatic test generation (atg) 3 and 5 volts operation; single or dual supply mode high speed performances: ? 505 ps max nand2 propagation delay at 4.5v, 825 ps at 2.7v and fo = 5 ? min 440 mhz toggle frequency at 4.5v, 230 mhz at 2.7v programmable pll available upon request high system frequency skew control through clock tree synthesis software low power consumption: ? 2.7 w/gate/mhz at 5v ? 0.86 w/gate/mhz at 3v integrated power on reset matrices with a max of 360 fully programmable pads standard 3, 6, 12 and 24 ma i/os versatile i/o cell: input, output, i/o, supply, oscillator cmos/ttl/pci interface esd (2 kv) and latch-up protected i/o high noise and emc immunity: ? i/o with slew rate control ? internal decoupling ? signal filtering between periphery and core ? application dependent supply routing and several independant supply sources wide selection of mqfps and mcga packages up to 352 pins delivery in die form with 110 m pad pitch advanced cad support: floor plan, proprietary delay models, timing driven layout, power management cadence ? , mentor ? , vital ? and synopsys ? reference platforms edif and vhdl reference formats available in military and space quality grades (scc, mil-prf-38535) latch-up immune total dose better than 300k rads (tm1019.5) qml q and v with smd 5962-00b03 and 5962-03b01 description the MG2RTP series is a 0.5 micron, array based, cmos product family. several arrays up to 270k gates cover most system integration needs. the MG2RTP is manu- factured using a 0.5 micron drawn, 3 metal layers cmos process, called scmos 3/2 rtp. the base cell architecture of the MG2RTP series provides high routability of logic with extremely dense compiled memories: ram and dpram. rom can be generated using synthesis tools. accurate control of clock distribution can be achieved by pll hardware and cts (clock tree synthesis) software. new noise prevention techniques are applied in the array and in the periphery: three or more independent supplies, internal decoupling, customization dependent supply routing, noise filtering, skew controlled i/os, low swing differential i/os, all contribute to improve the noise immunity and reduce the emission level. the MG2RTP is supported by an advanced software environment based on industry standards linking proprietary and commercial tools. verilog, modelsym and design compiler are the reference front end tools. floor planning associated with timing driven layout provides a short back end cycle. rad hard 190k used gates 0.5 m cmos sea of gates MG2RTP
2 MG2RTP 4116h?aero?06/03 the MG2RTP library allows straight forward migration from the mg1, mg1rt, mg2 and mg2rt sea of gates. a netlist based on this library can be simulated as either MG2RTP or mg2rt. it can also be simulated as mg2, provided there are no seu free cells. table 1. list of available MG2RTP matrices libraries the MG2RTP cell library has been designed to take full advantage of the features offered by both logic and test synthesis tools. design testability is assured by the full support of scan, jtag (ieee 1149) and bist methodologies. more complex macro functions are available in vhdl, such as two-wire interface (twi), uart, timer. block generators block generators are used to create a customer specific simulation model and metallisa- tion pattern for regular functions like ram and dpram. the basic cell architecture allows one bit per cell for ram and dpram. the main characteristics of these genera- tors are summarized below. type total gates typical usable gates maximum programmable i/os total pads mg2044p 44616 31200 146 165 mg2142p 142128 99500 262 281 mg2270p 270015 189000 360 377 function maximum size (bits) bits/word typical characteristics (16k bits) at5v access time (ns) used cells ram 32k 1-36 12 20k dpram 32k 1-36 14 23k
3 MG2RTP 4116h?aero?06/03 i/o buffer interfacing i/o flexibility all i/o buffers may be configured as input, output, bi-directional, oscillator or supply. a level translator is located close to each buffer. inputs input buffers with cmos or ttl thresholds are non inverting and feature versions with and without hysteresis. the cmos and ttl input buffers may incorporate pull-up or pull down terminators. for special purposes, a buffer allowing direct input to the matrix core is available. outputs several kinds of cmos and ttl output drivers are offered: fast buffers with 3, 6, 12 and 24 ma drive at 5v, low noise buffers with 12 ma drive at 5v. clock generation and pll clock generation atmel offers 5 different types of oscillators: 3 high frequency crystal oscillators and 2 rc oscillators. for all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10 ms. pll contact factory. frequency (mhz) typical consumption (ma) oscillators max 5v max 3v 5v 3v xtal 7m 10 6 1.2 0.4 xtal 50m 60 35 7 2 xtal 100m 120 70 16 5 rc 10m 10 10 2 1 rc 32m 32 32 3 1.5
4 MG2RTP 4116h?aero?06/03 power supply and noise protection the speed and density of the scmos3/2rtp technology causes large switching cur- rent spikes for example when: either 16 high current output buffers switch simultaneously or 10% of the 270 000 gates are switching within a window of 1 ns. sharp edges and high currents cause some parisitic elements in the packaging to become significant. in this frequency range, the package inductance and series resis- tance should be taken into account. it is known that an inductor slows down the settling time of the current and causes voltage drops on the power supply lines. these drops can affect the behavior of the circuit itself or disturb the external application (ground bounce). in order to improve the noise immunity of the mg core matrix, several mechanisms have been implemented inside the mg arrays. two kinds of protection have been added: one to limit the i/o buffer switching noise and the other to protect the i/o buffers against the switching noise coming from the matrix. i/o buffers switching protection three features are implemented to limit the noise generated by the switching current: the power supplies of the input and output buffers are separated. the rise and fall times of the output buffers can be controlled by an internal regulator. a design rule concerning the number of buffers connected on the same power supply line has been imposed. matrix switching current protection this noise disturbance is caused by a large number of gates switching simultaneously. to allow this without impacting the functionality of the circuit, three new features have been added: decoupling capacitors are integrated directly on the silicon to reduce the power supply drop. a power supply network has been implemented in the matrix. this solution reduces the number of parasitic elements such as inductance and resistance and constitutes an artificial vdd and ground plane. one mesh of the network supplies approximately 150 cells. a low pass filter has been added between the matrix and the input to the output buffer. this limits the transmission of the noise coming from the ground or the vdd supply of the matrix to the external world via the output buffers.
5 MG2RTP 4116h?aero?06/03 power consumption the power consumption of an MG2RTP array is due to three factors: leakage (p1), core (p2) and i/o (p3) consumption. p = p1 + p2 + p3 leakage (standby) power consumption the consumption due to leakage currents is defined as: p1 = (vdd - vss) * i ccsb * n cell where i ccsb is the leakage current through a polarized basic gate and n cell is the num- ber of used cells. core power consumption the power consumption due to the switching of cells in the core of the matrix is defined as: p2 = n cell * p gate * c activity * f where n cell is the number of used cells, f the data toggling frequency, which is equal to half the clock frequency for random data, p gate is the power consumption per cell and c activity is the fraction of the total number of cells toggling per cycle. p gate = p ca + p co capacitance power p ca = c * (vdd - vss) 2 /2 c is the total output capacitance and may be expressed as the sum of the drain capaci- tance of the driver, the wiring capacitance and the gate capacitance of the inputs. worst case value: p ca # 1.8 w/gate/mhz at 5v commutation power p co = (vdd - vss) * i dsohm where i dsohm is the current flowing into the driver between supply and ground during the commutation. i dsohm is about 15% of the pmos saturation current. worst case value: p co # 0.7 w/gate/mhz at 5v i/o power consumption the power consumption due to the i/os is: p3 = ni * c o * (vdd - vss) 2 * fi/2 with ni equals to the number of buffers running at fi and c o is the output capacitance. note: if a signal is a clock, fi = f, if it is a data with random values, fi = f/4.
6 MG2RTP 4116h?aero?06/03 table 2. typical power consumption example matrix mg2270p at 5v mg2270p at 3v used gates (70%) 190k 190k clock frequency 10 mhz 10 mhz standby power iccsb (125 c) 1 na 1 na p1 = (vdd - vss) * i ccsb * n cell 1 mw 0.6 mw core power power consumption per cell 2.7 w/gate/mhz 0.86 w/gate/mhz c activity 20% 20% p2 = n cell * p gate * c activity * f 1026 mw 327 mw i/o power total number of buffers 360 360 number of outputs and i/o buffers (ni) 100 100 output capacitance 50 pf 50 pf p3 = ni * c o * (vdd - vss) 2 * fi/2 625 mw 625 mw total power p = p1 + p2 + p3 1.65w 0.95w
7 MG2RTP 4116h?aero?06/03 packaging atmel offers a wide range of packaging options which are listed below: note: 1. contact atmel local design centers to check the availability of the matrix/package combination. package type (1) pins min/max lead spacing (mils) mqfp 100 352 2 5 . 6 20 mcga 349 50
8 MG2RTP 4116h?aero?06/03 design flows and tools design flows and modes a generic design flow for an MG2RTP array is illustrated below. a top down design methodology is proposed which starts with high level system descrip- tion and is refined in successive design steps. at each step, structural verification is performed which includes the following tasks: gate level logic simulation and comparison with high level simulation results. design and test rules check. power consumption analysis. timing analysis (only after floor plan). the main design stages are: system specification, preferably in vhdl form. functional description at rtl level. logic synthesis. floor planning and bonding diagram generation. test/scan insertion, atg and/or fault simulation. physical cell placement, jtag insertion and clock tree synthesis. routing to meet the various requirements of designers, several interface levels between the customer and atmel are possible. for each of the possible design modes a review meeting is required for data transfer from the user to atmel. in all cases the final routing and verifications are performed by atmel. the design acceptance is formalized by a design review which authorizes atmel to pro- ceed with sample manufacturing.
9 MG2RTP 4116h?aero?06/03 figure 1. MG2RTP design flow system specifications rtl simulation logic synthesis floor plan scan insertion atg and fault simulation jtag insertion clock tree synthesis routing + extract backannotated simulation sign-off samples manufacturing and test gate level placement simulation bonding diagram
10 MG2RTP 4116h?aero?06/03 design tools and design kits (dk) the basic content of a design kit is described in the table below. the interface formats to and from atmel rely on ieee or industry standard: vhdl for functional descriptions vhdl or edif for netlists tabular, log or .vcd for simulation results sdf (vital format) and spf for back annotation lef and def for physical floor plan information the design kits supported for several commercial tools are listed below. design kit support cadence/verilog (rtl and gate), logic design planner mentor/modelsim (rtl and gate), velocity, bsd architect, flex test synopsys, design compiler, primetime vital table 3. design kit description design tool or library atmel software name third party tools design manual and libraries - (1) synthesis library - (1) gate level simulation library - (1) design rules analyser star power consumption analyser comet floor plan library - (1) timing analyser library - (1) package and bonding software pim scan path and jtag insertion (1) atg and fault simulation library - (1) note: 1. refer to ?design kits cross reference tables? atd-ts-wf-r0181
11 MG2RTP 4116h?aero?06/03 electrical characteristics absolute maximum ratings dc characteristics ambient temperature under bias (ta) military ...................................................... -55 to +125 c junction temperature..............................tj < ta + 20 c storage temperature................................. -65 to +150 c ttl/cmos: supply voltage vdd ................................... -0.5v to +7v i/o voltage ......................................-0.5v to vdd + 0.5v note: stresses above those listed may cause permanent damage to the device. exposure to absolute maxi- mum rating conditions for extended period may affect device reliability. table 4. dc charateristics - specified at vdd = +5v 10% symbol parameter min typ max unit conditions vil input low voltage cmos input ttl input 0 0 -0.3 vdd 0.8 v- vih input high voltage cmos input ttl input 0.7 vdd 2.2 -vdd vdd v - vol output low voltage cmos ttl -- 1.9 0.4 v iol = 24, 12, 6, 3 ma (1) voh output high voltage cmos ttl 3.9 2.4 -- v ioh = 24, -12, -6, -3 ma (1) vt+ schmitt trigger positive threshold cmos input ttl input -- 3.3 1.5 v- vt- schmitt trigger negative threshold cmos input ttl input 1.1 0.9 -- v - deltav cmos hysterisis 25c/5v ttl hysterisis 25c/5v 1.9 0.6 v il input leakage no pull up/down pull up pull down -5 -44 75 -66 118 +5 -100 300 a a a - ioz 3-state output leakage current -5 +5 a- ios output short circuit current iosn iosp 48 36 - ma ma bout12 vout = 4.5v vout = vss iccsb leakage current per cell - 1.0 10.0 na - iccop operating current per cell - 0.39 0.53 a/mhz - note: 1. according buffer: bout24, bout12, bout6, bout3.
12 MG2RTP 4116h?aero?06/03 table 5. dc characteristics specified at vdd = +3v 0.3v symbol parameter min typ max unit conditions vil input low voltage lvcmos input lvttl input 0 0 ?0.3 vdd 0.8 v ? vih input high voltage lvcmos input lvttl input 0.7 vdd 2.0 ? vdd vdd v ? vol output low voltage ttl -? 0.4 v iol = -6, 3, 1.5 ma (1) voh output high voltage ttl 2.4 ?- v ioh = -4, 2, 1 ma (1) vt+ schmitt trigger positive threshold lvcmos input lvttl input ?? 2 1 v ? vt- schmitt trigger negative threshold lvcmos input lvttl input 0.8 0.7 ?? v ? deltav lvcmos hysterisis 25c/3v lvttl hysterisis 25c/3v 0.8 0.2 v il input leakage no pull up/down pull up pull down -1 -16 31 -20 42 +1 -50 140 a a a ? ioz 3-state output leakage current ? ? 1 a? ios output short circuit current iosn iosp 24 12 ?m ma bout12 vout = vdd vout = vss iccsb leakage current per cell ? 0.6 5 na ? iccop operating current per cell ? 0.2 - a/mhz ? note: 1. according buffer: bout12, bout6, bout3
13 MG2RTP 4116h?aero?06/03 ac characteristics table 6. ac characteristics - tj = 25 c, process typical (all values in ns) buffer description load transition vdd 5v 3v bout12 output buffer with 12 ma drive 60 pf tplh 3.332 5.277 tphl 2.131 2.842 bout3 output buffer with 3 ma drive 60 pf tplh 5.358 8.512 tphl 3.436 4.440 boutq low noise output buffer with 12 ma drive 60 pf tplh 3.742 5.696 tphl 5.515 8.616 b3sta3 3-state output buffer with 3 ma drive 60 pf tplh 5.468 8.622 tphl 3.510 4.617 b3sta12 3-state output buffer with 12 ma drive 60 pf tplh 3.475 5.426 tphl 2.195 2.990 b3staq low noise 3-state output buffer with 12 ma drive 60 pf tplh 3.703 5.776
14 MG2RTP 4116h?aero?06/03 table 7. ac characteristics - tj = 25 c, process typical (all values in ns) cell description load transition vdd 5v 3v bincmos cmos input buffer 15 fan tplh 0.936 1.430 tphl 0.776 1.085 binttl ttl input buffer 16 fan tplh 0.983 1.423 tphl 0.687 1.081 inv inverter 12 fan tplh 0.564 0.864 tphl 0.382 0.487 nand2 2 - input nand 12 fan tplh 0.726 1.076 tphl 0.599 0.809 fdff d flip-flop, clk to q 8 fan tplh 1.011 1.504 tphl 0.889 1.360 ts 0.400 0.615 th -0.158 -0.290 buf4x high drive internal buffer 51 fan tplh 0.813 1.182 tphl 0.605 0.876 nor2 2-input nor gate 8 fan tplh 0.722 1.204 tphl 0.347 0.433 oai22 4-input or and invert gate 8 fan tplh 0.773 1.287 tphl 0.398 0.510 osff d flip-flop with scan input, clk to q 8 fan tplh 0.981 1.462 tphl 1.143 1.656 ts 0.501 0.976 th -0.480 -0.791
printed on recycled paper. disclaimer: atmel corporation makes no warranty for the use of its products, other than those expressly contained in the company?s standar d warranty which is detailed in atmel?s terms and conditions located on the company?s web site. the company assumes no responsibi lity for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time wi thout notice, and does not make any commitment to update the information contained herein. no licenses to patents or other intellectual property of atmel are granted by the company in connection with the sale of atmel products, expressly or by implication. atmel?s products are not aut horized for use as critical components in life support devices or systems. atmel corporation atmel operations 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 487-2600 regional headquarters europe atmel sarl route des arsenaux 41 case postale 80 ch-1705 fribourg switzerland tel: (41) 26-426-5555 fax: (41) 26-426-5500 asia room 1219 chinachem golden plaza 77 mody road tsimshatsui east kowloon hong kong tel: (852) 2721-9778 fax: (852) 2722-1369 japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 memory 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 microcontrollers 2325 orchard parkway san jose, ca 95131 tel: 1(408) 441-0311 fax: 1(408) 436-4314 la chantrerie bp 70602 44306 nantes cedex 3, france tel: (33) 2-40-18-18-18 fax: (33) 2-40-18-19-60 asic/assp/smart cards zone industrielle 13106 rousset cedex, france tel: (33) 4-42-53-60-00 fax: (33) 4-42-53-60-01 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 scottish enterprise technology park maxwell building east kilbride g75 0qr, scotland tel: (44) 1355-803-000 fax: (44) 1355-242-743 rf/automotive theresienstrasse 2 postfach 3535 74025 heilbronn, germany tel: (49) 71-31-67-0 fax: (49) 71-31-67-2340 1150 east cheyenne mtn. blvd. colorado springs, co 80906 tel: 1(719) 576-3300 fax: 1(719) 540-1759 biometrics/imaging/hi-rel mpu/ high speed converters/rf datacom avenue de rochepleine bp 123 38521 saint-egreve cedex, france tel: (33) 4-76-58-30-00 fax: (33) 4-76-58-34-80 e-mail literature@atmel.com web site http://www.atmel.com 4116h?aero?06/03 /xm ? atmel corporation 2003 . all rights reserved. atmel ? and combinations thereof are the registered trademarks of atmel corporation or its subsidiaries. c adence is a trademark of cadence design systems. design compiler is a registered trademark of synopsis incorporated. synopsis is a registered trademark of synopsis incorpo- rated. mentor is a trademark of mentor graphics. other terms and product names may be the trademarks of others.

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